Verified Commit 8250e333 authored by René Kost's avatar René Kost
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Fix img align, fix todos

parent 0f6f652a
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......@@ -104,7 +104,7 @@ Note that each processing core includes it's own PMU.
\subsection{Internal Structure}
\label{sec:pmu-internal-structure}
\begin{figure}
\begin{figure}[H]
\centering
\includegraphics[width=0.95\textwidth]{img/PMU/100-animate.png}
\caption[Caption for LOF]{PMU in an ARM Cortex-A710 core. Own work, core design by \cite{arm2021CortexA710}}
......@@ -119,7 +119,7 @@ The main component of a PMU is a number of HPCs which are subdivided into a conf
Each HPC can be configured to monitor any given PME available in the CPU core \cite{arm2021CortexA710}.
Depending on the CPU model and platform a PMU only includes a limited number of HPCs due to space constraints.
While the \textit{ARM Cortex-A710} core design features 11 fully configurable HPCs \cite{arm2021CortexA710}, most modern Intel core designs only feature 2 fully configurable HPCs as well as 3 fixed function HPCs \todo{reference needed}.
While the \textit{ARM Cortex-A710} core design features 11 fully configurable HPCs \cite{arm2021CortexA710}, most modern Intel core designs only feature 2 to 4 fully configurable HPCs as well as 3 fixed function HPCs \cite{woo2021hardware}.
\subsection{Programming Interface}
\label{sec:pmu-api}
......@@ -143,18 +143,18 @@ This section will first show the experiment setup used by Leng et al, following
\subsection{Experiment setup}
\label{sec:data-experiment}
\begin{figure}
Introducing a SSF into real-world CPU hardware is hardly possible due to the transistor size.
Leng et al therefore proposes to not use real CPUs but to simulate software execution with and without SSFs in a simulation environment \cite{leng2017hardware}.
They decided to use \textit{GemFI} which is a fault injection tool developed for testing applications on unreliable substrates \cite{parasyris2014gemfi}.
GemFI itself is based on Gem5, a popular cycle-accurate CPU simulation tool that supports most commercial ISAs \cite{binkert2011gem5}.
\begin{figure}[H]
\centering
\includegraphics[width=0.7\textwidth]{img/GemFI-data-analysis-pipeline.png}
\caption[Caption for LOF]{Abstract experiment setup used to gather PME data with and without SSFs using the simulator GemFI.}
\label{img:experiment-setup}
\end{figure}
Introducing a SSF into real-world CPU hardware is hardly possible due to the transistor size.
Leng et al therefore proposes to not use real CPUs but to simulate software execution with and without SSFs in a simulation environment \cite{leng2017hardware}.
They decided to use \textit{GemFI} which is a fault injection tool developed for testing applications on unreliable substrates \cite{parasyris2014gemfi}.
GemFI itself is based on Gem5, a popular cycle-accurate CPU simulation tool that supports most commercial ISAs \cite{binkert2011gem5}.
\Cref{img:experiment-setup} shows the abstract experiment setup.
The general idea is to first execute a given binary on a simulated CPU without any anomalies and then execute the same binary again on the same hardware but with SSFs introduced to all CPU pipeline stages.
While the simulation is running, selected PMEs are being sampled over time to create a time series for later analysis (see \cref{sec:data-analysis}).
......@@ -232,7 +232,7 @@ Generating the necessary data for a given real-world processor might therefore b
\subsection{Application complexity}
Another problem that I see is that the Leng et al only considers very basic applications originating from the \textit{MiBench} \todo{ref?} benchmark suite for anomaly detection.
Another problem that I see is that the Leng et al only considers very basic applications originating from the \textit{MiBench} benchmark suite as presented in \cite{guthaus2001mibench} for anomaly detection.
As an example, the qsort benchmark was used only with the very same input data.
This makes it very easy to detect anomalies in the resulting data but does not necessarily show a real world use case of the qsort algorithm.
......
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