From 7d859ff4937a22aabc0d3f352d1f515fb8b38528 Mon Sep 17 00:00:00 2001 From: Kyoungil Kim <ki0351.kim@samsung.com> Date: Wed, 23 May 2012 21:29:51 +0900 Subject: [PATCH] spi: Change FIFO flush operation and spi channel off Setting SW_RST does TX/RX FIFO flush. After FIFO flush, SW_RST should be cleared. The above setting and clearing SW_RST operation should be done after spi channel off. Signed-off-by: Kyoungil Kim <ki0351.kim@samsung.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca> --- drivers/spi/spi-s3c64xx.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 88c3f5e51c36..ad93231a8038 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -214,6 +214,10 @@ static void flush_fifo(struct s3c64xx_spi_driver_data *sdd) writel(0, regs + S3C64XX_SPI_PACKET_CNT); + val = readl(regs + S3C64XX_SPI_CH_CFG); + val &= ~(S3C64XX_SPI_CH_RXCH_ON | S3C64XX_SPI_CH_TXCH_ON); + writel(val, regs + S3C64XX_SPI_CH_CFG); + val = readl(regs + S3C64XX_SPI_CH_CFG); val |= S3C64XX_SPI_CH_SW_RST; val &= ~S3C64XX_SPI_CH_HS_EN; @@ -248,10 +252,6 @@ static void flush_fifo(struct s3c64xx_spi_driver_data *sdd) val = readl(regs + S3C64XX_SPI_MODE_CFG); val &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON); writel(val, regs + S3C64XX_SPI_MODE_CFG); - - val = readl(regs + S3C64XX_SPI_CH_CFG); - val &= ~(S3C64XX_SPI_CH_RXCH_ON | S3C64XX_SPI_CH_TXCH_ON); - writel(val, regs + S3C64XX_SPI_CH_CFG); } static void s3c64xx_spi_dmacb(void *data) -- GitLab