Adding gem5 source to svn.

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1819 8c4709b5-6ec9-48aa-a5cd-a96041d1645a

.gitignore

@@ -5,6 +5,7 @@
 *.pb.h
 *.pb.cc
 *.gcda
+*.pyc
 *~
 Makefile
 build
@@ -27,4 +28,4 @@ simulators/bochs/ltdlconf.h
 
 !simulators/bochs/plex86/kernel/freebsd/Makefile
 
-simulators/gem5/*
+simulators/gem5/.hg

simulators/gem5/.hgignore

+syntax: glob
+build
+parser.out
+parsetab.py
+cscope.files
+cscope.out
+*.pyc
+*~
+.*.swp
+m5out
+src/doxygen

simulators/gem5/.hgtags

+6b99127531fd692ff0f202e327d0826ed2bfcf5f m5_1.0_beta1
+1a40e60270c11ec24f11c783e70367e2740cdc56 m5_1.0_beta1
+069849384988e553b6edae71ecaf1fb6e918d738 m5_1.0_beta2
+4cfa92eca35d532b339507f1c631e1986d87b258 m5_1.0_tutorial
+ffe1942d845c67fb3fd04692420c9433638eba13 m5_1.0_web
+af8bf5e4e85ba1a773183cc3f6c43bcdf0ce146a m5_1.1
+1c0eeb0dae9b6a2a5479faf3ab52fb1ed0ce703f m5_1.1
+c486924ed90eb6805e8cf44ddee5ad5435c79051 m5_1.1
+01e679b66ca9474f10f8f96d391693adf76fc73a m5_1.1
+2608cd7def85c9fdc84251295c8023fab990d530 m5_1.1
+cdd48642d9bf584bd445b40abec9e7f934a5900b m5_1.1
+8d690c7c2efced99f7991b7ace56d769bae7cfdd m5_2.0_beta1
+d83885ad2b41777c97b94882aa8f07e761e55ac1 m5_2.0_beta1_patch1
+1906dcace7c27b2153bfb95ca1218660e1cc1f70 m5_2.0_beta2
+b174ae14f007ba0c341f8df77d36f57f48369cc8 m5_2.0_beta2
+91a9ac67662aa3a79315ade29b17a85961fecd88 m5_2.0_beta3
+dce5a8655829b7d2e24ce40cafc9c8873a71671f m5_2.0_beta5
+1ac44b6c87ec71a8410c9a9c219269eca71f8077 m5_2.0_beta4
+60a931b03fb165807f02bcccc4f7d0fd705a67a9 copyright_update
+d8b246a665c160a31751b4091f097022cde16dd7 m5_2.0_beta6
+5de565c4b7bdf46670611858b709c1eb50ad7c5c Calvin_Submission

simulators/gem5/COPYING

+Please see individual files for details of the license on each file.
+The preferred license can be found in LICENSE.
+
+All files in this distribution (other than in the ext directory) have
+licenses based on the BSD or MIT licenses.  Some files in the ext
+directory are GNU LGPL.  No other licenses are found in this
+distribution.
+
+Beyond the BSD license, some files include the following clarification
+of the license as required by the copyright holder:
+
+    The license below extends only to copyright in the software and
+    shall not be construed as granting a license to any other
+    intellectual property including but not limited to intellectual
+    property relating to a hardware implementation of the
+    functionality of the software licensed hereunder.  You may use the
+    software subject to the license terms below provided that you
+    ensure that this notice is replicated unmodified and in its
+    entirety in all distributions of the software, modified or
+    unmodified, in source code or in binary form.
+
+The copyright holders include (not counting the ext directory):
+
+Copyright (c) 2000-2011 The Regents of The University of Michigan
+Copyright (c) 1990,1993-1995,2007-2010 The Hewlett-Packard Development Company
+Copyright (c) 1999-2009,2011 Mark D. Hill and David A. Wood
+Copyright (c) 2009-2011 ARM Limited
+Copyright (c) 2008-2009 Princeton University
+Copyright (c) 2007 MIPS Technologies, Inc.
+Copyright (c) 2009-2011 Advanced Micro Devices, Inc.
+Copyright (c) 2009 The University of Edinburgh
+Copyright (c) 2007-2008 The Florida State University
+Copyright (c) 2010 Massachusetts Institute of Technology
+Copyright (c) 1990-1993 The Regents of the University of California
+Copyright (c) 2006-2009 Nathan Binkert
+Copyright (c) 2001 The NetBSD Foundation, Inc.
+Copyright (c) 2010-2011 Gabe Black
+Copyright (c) 1994 Adam Glass
+Copyright (c) 1990-1992 MIPS Computer Systems, Inc.
+Copyright (c) 2004 Richard J. Wagner
+Copyright (c) 2000 Computer Engineering and Communication Networks Lab
+Copyright (c) 2001 Eric Jackson
+Copyright (c) 1990 Hewlett-Packard Development Company
+Copyright (c) 1994-1996 Carnegie-Mellon University.
+Copyright (c) 1993-1994 Christopher G. Demetriou
+Copyright (c) 1997-2002 Makoto Matsumoto and Takuji Nishimura
+Copyright (c) 1998,2001 Manuel Bouyer.

simulators/gem5/LICENSE

+Copyright (c) <date> <copyright holder>
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are
+met: redistributions of source code must retain the above copyright
+notice, this list of conditions and the following disclaimer;
+redistributions in binary form must reproduce the above copyright
+notice, this list of conditions and the following disclaimer in the
+documentation and/or other materials provided with the distribution;
+neither the name of the copyright holders nor the names of its
+contributors may be used to endorse or promote products derived from
+this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

simulators/gem5/README

+This is the M5 simulator.
+
+For detailed information about building the simulator and getting
+started please refer to http://www.m5sim.org.
+
+Specific pages of interest are:
+http://www.m5sim.org/wiki/index.php/Compiling_M5
+http://www.m5sim.org/wiki/index.php/Running_M5
+
+Short version:
+
+1. If you don't have SCons version 0.98.1 or newer, get it from
+http://wwww.scons.org.
+
+2. If you don't have SWIG version 1.3.31 or newer, get it from
+http://wwww.swig.org.
+
+3. Make sure you also have gcc version 3.4.6 or newer, Python 2.4 or newer
+(the dev version with header files), zlib, and the m4 preprocessor.
+
+4. In this directory, type 'scons build/ALPHA_SE/tests/debug/quick'.  This
+will build the debug version of the m5 binary (m5.debug) for the Alpha
+syscall emulation target, and run the quick regression tests on it.
+
+If you have questions, please send mail to m5-users@m5sim.org
+
+WHAT'S INCLUDED (AND NOT)
+-------------------------
+
+The basic source release includes these subdirectories:
+ - m5:
+   - configs: simulation configuration scripts
+   - ext: less-common external packages needed to build m5
+   - src: source code of the m5 simulator
+   - system: source for some optional system software for simulated systems
+   - tests: regression tests
+   - util: useful utility programs and files
+
+To run full-system simulations, you will need compiled system firmware
+(console and PALcode for Alpha), kernel binaries and one or more disk images. 
+These files for Alpha are collected in a separate archive, m5_system.tar.bz2.
+This file can he downloaded separately.
+
+Depending on the ISA used, M5 may support Linux 2.4/2.6, FreeBSD, and the
+proprietary Compaq/HP Tru64 version of Unix. We are able to distribute Linux
+and FreeBSD bootdisks, but we are unable to distribute bootable disk images of
+Tru64 Unix. If you have a Tru64 license and are interested in
+obtaining disk images, contact us at m5-users@m5sim.org

simulators/gem5/build_opts/ALPHA

+TARGET_ISA = 'alpha'
+SS_COMPATIBLE_FP = 1
+CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU'
+PROTOCOL = 'MI_example'

simulators/gem5/build_opts/ALPHA_MESI_CMP_directory

+SS_COMPATIBLE_FP = 1
+CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU'
+PROTOCOL = 'MESI_CMP_directory'

simulators/gem5/build_opts/ALPHA_MOESI_CMP_directory

+SS_COMPATIBLE_FP = 1
+CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU'
+PROTOCOL = 'MOESI_CMP_directory'

simulators/gem5/build_opts/ALPHA_MOESI_CMP_token

+SS_COMPATIBLE_FP = 1
+CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU'
+PROTOCOL = 'MOESI_CMP_token'

simulators/gem5/build_opts/ALPHA_MOESI_hammer

+SS_COMPATIBLE_FP = 1
+CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU'
+PROTOCOL = 'MOESI_hammer'

simulators/gem5/build_opts/ALPHA_Network_test

+SS_COMPATIBLE_FP = 1
+CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU'
+PROTOCOL = 'Network_test'

simulators/gem5/build_opts/ARM

+TARGET_ISA = 'arm'
+CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU'
+PROTOCOL = 'MI_example'

simulators/gem5/build_opts/MIPS

+TARGET_ISA = 'mips'
+CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU'
+PROTOCOL = 'MI_example'

simulators/gem5/build_opts/NOISA

+TARGET_ISA = 'no'
+CPU_MODELS = 'no'

simulators/gem5/build_opts/POWER

+TARGET_ISA = 'power'
+CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU'
+PROTOCOL = 'MI_example'

simulators/gem5/build_opts/SPARC

+TARGET_ISA = 'sparc'
+CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU'
+PROTOCOL = 'MI_example'

simulators/gem5/build_opts/X86

+TARGET_ISA = 'x86'
+CPU_MODELS = 'AtomicSimpleCPU,O3CPU,TimingSimpleCPU'
+PROTOCOL = 'MI_example'

simulators/gem5/build_opts/X86_MESI_CMP_directory

+TARGET_ISA = 'x86'
+CPU_MODELS = 'TimingSimpleCPU,O3CPU'
+PROTOCOL = 'MESI_CMP_directory'