Additionally passing the current Bochs CPU context and instruction cache entry...
Additionally passing the current Bochs CPU context and instruction cache entry to BochsController (enables detailed instruction analysis and modification) git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1361 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
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- doc/class-diagram.dia 249 additions, 10 deletionsdoc/class-diagram.dia
- doc/class-diagram.png 0 additions, 0 deletionsdoc/class-diagram.png
- simulators/bochs/cpu/cpu.cc 2 additions, 2 deletionssimulators/bochs/cpu/cpu.cc
- src/core/sal/bochs/BochsController.cc 9 additions, 28 deletionssrc/core/sal/bochs/BochsController.cc
- src/core/sal/bochs/BochsController.hpp 14 additions, 1 deletionsrc/core/sal/bochs/BochsController.hpp
- src/core/sal/bochs/Breakpoints.ah 2 additions, 2 deletionssrc/core/sal/bochs/Breakpoints.ah
- src/experiments/l4-sys/campaign.cc 37 additions, 22 deletionssrc/experiments/l4-sys/campaign.cc
- src/experiments/l4-sys/campaign.hpp 2 additions, 0 deletionssrc/experiments/l4-sys/campaign.hpp
- src/experiments/l4-sys/experiment.cc 314 additions, 166 deletionssrc/experiments/l4-sys/experiment.cc
- src/experiments/l4-sys/experiment.hpp 40 additions, 5 deletionssrc/experiments/l4-sys/experiment.hpp
- src/experiments/l4-sys/experimentInfo.hpp 17 additions, 7 deletionssrc/experiments/l4-sys/experimentInfo.hpp
- src/experiments/l4-sys/l4sys.proto 15 additions, 7 deletionssrc/experiments/l4-sys/l4sys.proto
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