Important bugfix: passing the instruction cache entry pointer
does not account for arrays of instructions provided by one virtual instruction trace cache entry -> passing the current instruction directly. ALUInstr not yet completely tested. git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1704 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
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- simulators/bochs/cpu/cpu.cc 2 additions, 2 deletionssimulators/bochs/cpu/cpu.cc
- src/core/sal/bochs/BochsController.cc 5 additions, 5 deletionssrc/core/sal/bochs/BochsController.cc
- src/core/sal/bochs/BochsController.hpp 3 additions, 3 deletionssrc/core/sal/bochs/BochsController.hpp
- src/core/sal/bochs/Breakpoints.ah 2 additions, 2 deletionssrc/core/sal/bochs/Breakpoints.ah
- src/experiments/l4-sys/CMakeLists.txt 1 addition, 0 deletionssrc/experiments/l4-sys/CMakeLists.txt
- src/experiments/l4-sys/UDIS86.cc 1 addition, 1 deletionsrc/experiments/l4-sys/UDIS86.cc
- src/experiments/l4-sys/UDIS86.hpp 2 additions, 2 deletionssrc/experiments/l4-sys/UDIS86.hpp
- src/experiments/l4-sys/aluinstr.hpp 154 additions, 70 deletionssrc/experiments/l4-sys/aluinstr.hpp
- src/experiments/l4-sys/campaign.cc 26 additions, 9 deletionssrc/experiments/l4-sys/campaign.cc
- src/experiments/l4-sys/experiment.cc 95 additions, 54 deletionssrc/experiments/l4-sys/experiment.cc
- src/experiments/l4-sys/experiment.hpp 10 additions, 1 deletionsrc/experiments/l4-sys/experiment.hpp
- src/experiments/l4-sys/experimentInfo.hpp 5 additions, 6 deletionssrc/experiments/l4-sys/experimentInfo.hpp
- src/experiments/l4-sys/l4sys.proto 22 additions, 10 deletionssrc/experiments/l4-sys/l4sys.proto
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